1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a great number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Thus, relatively high leakage currents are caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer and may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, also appropriate metal-containing materials may have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided. The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence since, for instance, the adjustment of an appropriate work function for the transistors of different conductivity type and the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein, in the typical electrode material, polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in combination with the electrode metal may be required. In other very promising approaches, the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing may be based on the plurality of well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon and silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques. On the other hand, the gate electrode stack and, in particular, the sensitive high-k dielectric materials, in combination with any metal-containing cap layers, have to be reliably confined by appropriate materials throughout the entire processing of the semiconductor device.
Further concepts for enhancing performance of transistors have been developed by providing a plurality of strain-inducing mechanisms in order to increase the charge carrier mobility in the channel regions of the various transistors. It is well known that charge carrier mobility in silicon may be efficiently increased by applying certain strain components, such as tensile and compressive strain for N-channel transistors and P-channel transistors, respectively, so that superior transistor performance may be obtained for an otherwise identical transistor configuration compared to non-strained silicon materials. For instance, efficient strain-inducing mechanisms may be implemented by incorporating a strained semiconductor material in the drain and source regions of transistors, for instance in the form of a silicon/germanium alloy, a silicon/carbon alloy and the like, wherein the lattice mismatch between the semiconductor alloy and the silicon base material may result in a tensile or compressive state, which in turn may induce a desired type of strain in the channel region of the transistor. Other efficient strain-inducing mechanisms are well established in which a highly stressed dielectric material may be positioned in close proximity to the transistor, thereby also inducing a certain type of strain in the channel region.
Although the approach of providing a sophisticated high-k metal gate electrode structure in an early manufacturing stage, possibly in combination with additional strain-inducing mechanisms, may have the potential of providing extremely powerful semiconductor devices, such as CPUs, storage devices, systems on a chip (SOC) and the like, conventional approaches may still suffer from process non-uniformities, as will be described with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate, in combination with a semiconductor layer 102, such as a silicon layer or a semiconductor material which contains a significant amount of silicon. In the manufacturing stage shown, the semiconductor device 100 comprises transistors 150A, 150B formed in and above respective active regions 102A and 102B. An active region is to be understood as a semiconductor region in the layer 102 in which PN junctions for one or more transistors are to be formed. An isolation structure 102C, such as a trench isolation, is provided in the semiconductor layer 102 and may be formed so as to be adjacent to the active region 102A, wherein it should be appreciated that the isolation structure 102C may also be provided laterally between the active regions 102A, 102B, thereby electrically isolating these regions, at least in the horizontal direction. Furthermore, a plurality of gate electrode structures 160A, 160B and 160C are formed above the semiconductor layer 102. In FIG. 1a, the gate electrode structures 160A, 160B are illustrated at a cross-section in which the gate electrode structures 160A, 160B are formed on the active regions 102A and 102B, respectively, wherein it should be appreciated that these gate electrode structures typically extend beyond the corresponding active region and thus these gate electrode structures may also be formed above the isolation region 102C. For example, the gate electrode structure 160C may  represent a corresponding portion of a gate electrode structure that may extend into an active region along the direction perpendicular to the drawing plane of FIG. 1a. In other cases, the gate electrode structure 160C may represent a portion of the gate electrode structure 160A. In other words, in this case, the gate electrode structure 160C may represent a “continuation” of the gate electrode structure 160A in a direction perpendicular to the drawing plane of FIG. 1a. At any rate, the gate electrode structure 160C may be formed above a portion of the isolation structure 102C, which is in close proximity to the active region 102A.
As previously discussed, the gate electrode structures may comprise a gate insulation layer 161 formed on the active regions 102A, 102B, respectively, and the gate insulation layer may comprise a high-k dielectric material, such as hafnium oxide-based materials and the like. It is to be noted that frequently the gate insulation layer 161 may additionally comprise a conventional dielectric material, such as a silicon oxide-based material, however, with a significantly reduced thickness of approximately 0.8 nm and less. Furthermore, a metal-containing material is typically formed on the gate insulation layer 161 when comprising the high-k dielectric material, wherein the corresponding metal-containing material may be provided with different material composition for transistors of different conductivity type in order to adjust an appropriate work function for the corresponding gate electrode structure. For example, a conductive cap layer 162A is provided in the gate electrode structures 160A, 160C, which may correspond to the same conductivity type of a transistor. Thus, the cap layer 162A typically has incorporated therein a work function metal species for the transistor 150A, while a conductive cap layer 162B includes an appropriate work function metal species for the transistor 150B. Furthermore, the gate electrode structures may comprise a further electrode material 163, such as silicon, silicon/germanium and the like, followed by a dielectric cap layer or layer system which, however, may have a different thickness for the gate electrode structures 160A, 160C on the one hand, and the gate electrode structure 160B on the other hand, due to a different exposure to reactive process atmospheres applied during the previous processing. Thus, the dielectric cap layers 164A of the structures 160C, 160A may have a thickness of, for instance, 20-40 nm, while the thickness of the cap layer 164B may be greater by approximately 15-25 nm.
Furthermore, a sidewall spacer structure 165, for instance comprising a liner material 165A in combination with a spacer element 165B, may be provided so as to protect the sidewalls of the electrode material 164, and in particular of the sensitive materials 162A, 162B and 161. The liner 165A and the spacer element 165B are typically comprised of silicon nitride. As illustrated, the materials of the components 165A, 165B may be provided in the form of a non-patterned layer system above the active region 102B and the gate electrode structure 160B so as to act as an efficient mask material during a process sequence for forming a strain-inducing semiconductor material 151, such as a silicon/germanium material, in the active region 102A. As discussed above, in sophisticated applications, performance of P-channel transistors may be significantly increased upon incorporating a strain-inducing silicon/germanium alloy into the active region of the P-channel transistor, since in this case a significant compressive strain may be induced in a channel region 152. It should be appreciated that, if required, a threshold adjusting semiconductor material, indicated as 152A, may be provided in the channel region 152, if required for appropriately adjusting the overall threshold voltage of the transistor 150A.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process strategies. After forming the isolation region 102C and, thus, laterally delineating the active regions 102A, 102B and any other active regions, the material layer 152A, if required, may be selectively formed in the active region 102A. Next, appropriate materials for the gate insulation layer 161 and the layers 162A, 162B may be formed by appropriate deposition techniques and patterning sequences, possibly in combination with any thermal treatments in order to diffuse a work function metal species into the gate dielectric layers 161, if considered appropriate. In other cases, a desired work function metal species may be deposited in the form of a continuous material layer, which may then be patterned so as to form a desired material layer above the corresponding active regions. Thereafter, the electrode material 163, for instance in the form of amorphous or polycrystalline silicon, is deposited by using well-established deposition techniques, followed by the deposition of the dielectric cap layer or layer system 164A, 164B. If required, any additional materials, such as anti-reflective coating (ARC) materials and the like, may be provided, if required, and a sophisticated lithography process sequence and anisotropic etch processes are applied in order to obtain the gate electrode structures 160A, 160B, 160C according to the design rules. For example, a length of the gate electrode structures, i.e., the horizontal extension of the electrode materials 162A, 162B, may be 50 nm and less. Next, the material layers 165S are deposited, for instance by thermally activated chemical vapor deposition (CVD), plasma enhanced CVD, low pressure CVD, multi-layer deposition techniques, in order to obtain the desired material characteristics. For example, silicon nitride may be deposited so as to form a dense liner, followed by the deposition of a further silicon nitride material for the spacer elements 165B. As discussed above, when adjusting the work function and thus the basic threshold voltage of the transistors 150A, 150B upon patterning the gate electrode structures 160A, 160B, a reliable confinement of the layers 161 and 162A, 162B has to be guaranteed during the further processing since any exposure to the active process atmospheres, such as oxygen-containing chemicals and the like, may result in a significant shift of the previously adjusted transistor characteristics.
Thereafter, an etch mask (not shown) is formed so as to cover the transistor 150B while exposing the active region 102A and the portion of the isolation region 102C having formed thereon the gate electrode structure 160C. As discussed above, the gate electrode structures 160A, 160C may represent one and the same gate electrode structure or structures that are provided in close proximity and correspond to an area of P-type transistors. During the corresponding anisotropic etch processes, well-established plasma-based recipes are applied so as to etch through the previously deposited layers 165S, thereby forming the spacer structure 165 on the gate electrode structures 160C, 160A. Moreover, the etch process may be continued so as to etch into the active region 102A, possibly on the basis of a changed etch chemistry in order to form cavities therein, which are subsequently filled with the material 151. Consequently, during the cavity etch process, also the cap layers 164A are exposed to the reactive etch ambient and may thus suffer from a pronounced material erosion, which may result in the reduced thickness of these layers compared to the dielectric cap layer 164B, which may still be covered by the spacer layer 165S and corresponding resist mask.
Next, the device 100 is prepared for the selective deposition of the strain-inducing semiconductor material 151, which typically involves a plurality of cleaning recipes, which may result in a significant erosion of oxide-based materials, such as the insulating material in the isolation region 102C. Thus, a pronounced degree of recessing, indicated as 107C, is generated in the isolation region 102C, thereby also causing a certain degree of under-etching of the spacer structure 165 of the gate electrode structure 160C. Thereafter, the material 151 is selectively grown in the corresponding cavities by applying a selective epitaxial growth process based on well-established process recipes. Typically, the process parameters are selected such that a significant degree of material deposition may occur on more or less pure silicon surface areas, while dielectric surface areas, such as silicon nitride, silicon dioxide and the like, may substantially not receive the material 151.
FIG. 1b schematically illustrates the semiconductor device 100 in a manufacturing stage in which an etch mask 103 covers the active region 102A and a portion of the isolation region 102C comprising the gate electrode structure 160C, while the gate electrode structure 160B and the active region 102B are exposed to a reactive etch ambient 104. During the etch process 104, the spacer structure 165 is formed on sidewalls of the gate electrode structure 160B. Thus, during the process 104, the dielectric cap layer 164B may be exposed, wherein, however, a significantly reduced degree of material erosion may occur so that still a significant difference in thickness between the layer 164B and the layers 164A is preserved. After the etch process 104, the etch mask 103 may be removed and thus the gate electrode structures 160A, 160C may have a similar configuration, i.e., these structures comprise the sidewall spacer structure 165, which may be used as an offset spacer structure for controlling a subsequent implantation sequence for introducing a dopant species in order to form drain and source extension regions and halo regions, i.e., counter-doped regions, as required for obtaining the complex dopant profile for adjusting the overall transistor characteristics. On the other hand, due to the previous difference in the overall process flow, the cap layers 164A and 164B may differ significantly from each other with respect to their thickness in this manufacturing stage. During the further processing, the dielectric cap layers 164A, 164B have to be removed, which, however, may influence the configuration of the spacer structure 165 if comprised of a similar material. For instance, plasma-based etch recipes or wet chemical etch recipes may be applied which, however, may have a pronounced lateral etch rate, thereby causing a significant degree of material erosion in the spacer structure 165. For this reason, the spacer structure 165 is protected by a sacrificial oxide spacer element having a high etch resistivity with respect to an efficient nitride etch chemistry.
FIG. 1c schematically illustrates the semiconductor device 100 with an oxide spacer layer 166, which is etched during an etch process 105 in order to form sacrificial oxide spacers 166S on the sidewall spacer structures 165. During the etch process 105, a significant material erosion may also occur in the isolation structure 102C since a certain over-etch time is required in order to reliably expose the dielectric cap layers 164A, 164B. Consequently, the recess 107C in the isolation region 102C may be significantly increased and also a certain degree of recessing 107A, 107B is generated in the active regions 102A, 102B, respectively. Consequently, also a certain amount of the strain-inducing material 151 is removed during the etch process 105.
FIG. 1d schematically illustrates the device 100 when exposed to a further etch process 106 for removing the dielectric cap layers 164A, 164B on the basis of an appropriate etch chemistry, such as hot phosphoric acid and the like. It should be appreciated that the pronounced recess 107C in the isolation region 102C may result in a certain probability of under-etching the gate electrode structure 160C and attacking the sensitive materials, which may be highly disadvantageous in any areas close to the active region 102A, for example when the gate electrode structure 160C is the continuation of the gate electrode structure 160A along the direction perpendicular to the drawing plane of FIG. 1e, or in other cases when the gate electrode structure 160C is formed laterally adjacent to the active region 102A, as shown in FIG. 1e, however, with a very reduced offset, as may be required in some sophisticated device designs.
FIG. 1e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the sacrificial sidewall spacers 166S (FIG. 1d) are removed, which may be accomplished on the basis of diluted hydrofluoric acid (HF) which, however, also removes a certain portion of the isolation structure 102C, thereby even further increasing the recess 107C.
As a result, after the process sequence for encapsulating the sensitive gate materials, forming the strain-inducing material 151 and removing the dielectric cap materials, a pronounced degree of recessing 107C is generated in the isolation region 102C, while also material removal has occurred in the active region 102A, thereby removing a certain amount of strain-inducing material 151, which in turn may result in less pronounced performance of the transistor 150A. Furthermore, the further processing has to be continued on the basis of large differences in surface topography, which may generally result in a high degree of non-uniformity of the corresponding process techniques, for instance for incorporating dopant species based on appropriate implantation masks, forming a further spacer structure so as to adjust the lateral and vertical dopant profile and finally forming an interlayer dielectric material, possibly comprising highly stressed dielectric material layers and the like. Moreover, since integrity of the sensitive gate materials may have deteriorated due to the pronounced recessing of the gate electrode structure 160C at areas in close proximity to a neighboring active region, also pronounced device failures may be observed when completing the transistors 150A, 150B according to a process strategy, as discussed before.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.